1. Field
Example embodiments relate to semiconductor chip structures, methods of manufacturing the semiconductor chip structures, a semiconductor chip package, and a method of manufacturing the semiconductor chip package. Other example embodiments relate to semiconductor chip structures that have improved adhesion strength by changing a structure of an insulation layer on a semiconductor chip, methods of manufacturing the semiconductor chip structures, a semiconductor chip package, and a method of manufacturing the semiconductor chip package.
2. Description of the Related Art
Generally, a semiconductor device may be manufactured in a fab process for forming semiconductor chips including electrical elements on a silicon wafer, used as a semiconductor substrate, an electrical die sorting (EDS) process for testing electrical characteristics of the semiconductor chips formed by the fab process, and a packaging process for encapsulating the semiconductor chips with an epoxy resin and for singularizing the semiconductor chips.
FIG. 1 is a cross-sectional view illustrating a conventional board-on-chip (BOC) package. Referring to FIG. 1, a conventional BOC package 1 may include a semiconductor chip 5 having pads. A first insulation layer 10 may be formed on the semiconductor chip 5 exposing the pads of the semiconductor chip 5. A redistribution layer 15 may be formed on the first insulation layer 10. The redistribution layer 15 may make contact with the pads. A second insulation layer 20 may be formed on the first insulation layer 10 and the redistribution layer 15 partially exposing the redistribution layer 15. An adhesive layer 25 may be formed on the second insulation layer 20. A printed substrate 30 may be placed on the adhesive layer 25 exposing the redistribution layer 15. A third insulation layer 35 may be formed on the printed substrate 30. Bonding wires 40 may electrically connect the redistribution layer 15 to the printed substrate 30. A molding layer 45 may cover the bonding wires 40. Solder balls 50 making contact with the printed substrate 30 may be formed on the third insulation layer 35.
In the conventional package, the first insulation layer 10, the redistribution layer 15, the second insulation layer 20, the adhesive layer 25 and the molding layer 45 may be interposed between the semiconductor chip 5 and the printed substrate 30. Because the above-mentioned layers include different materials that make contact with each other, adhesion strength between the above-mentioned layers may be relatively weak. Further, relatively large stress may be applied between the semiconductor chip 5 and the printed substrate 30. Therefore, peeling may generate between the first insulation layer 10 and the redistribution layer 15, the redistribution layer 15 and the second insulation layer 20, the second insulation layer 20 and the adhesive layer 25, and the adhesive layer 25 and the molding layer 45.